The Sort-Assemble-Blend Routing Problem and its Application to Semiconductors


For decades, the semiconductor industry norm – including those produced by Intel, the world’s largest semiconductor chip manufacturer – was to pack all required capabilities (such as memory, compute, and graphics) into a single monolithic design that was printed onto one single large die, packaged, and sold. Due to recent market and technological trends, product architectures have shifted from monolithic to modular designs. New semiconductor products combine multiple small die with dedicated functions into Multi-Die Packages (MDPs) that require assembly. This change increases complexity substantially but has two main advantages: (1) die yields increase, and (2) product quality improves. 

Semiconductor manufacturing is an inherently stochastic process in which layers of microscopic transistors are printed onto a silicon wafer from which individual die are cut. Defects caused by microscopic impurities occur randomly throughout the wafer, and can render a whole die unusable. Because of these random defects, die yields are inversely proportional to die area. For this reason, modular MDP designs favor smaller, function-specific die which can be combined into assemblies with equal functionality. 

Manufacturing stochasticity also affects performance properties of die, such as speed and power consumption. Two die from the same wafer can have vastly different performance characteristics. In a monolithic design, because all functionality is printed on a single large die, there are limited options for reducing variability in the final product. However, in a modular architecture, the MDP can be built by combining individual die whose performance characteristics complement each other. This strategy significantly improves product performance but introduces complexities of managing and routing materials since there are many ways to achieve desired outcomes.

Optimally building a range of modular products requires an efficient and scalable methodology. A standard approach used in semiconductor manufacturing is to test and sort each die and sub-assembly into distinct performance categories. Since the semiconductor manufacturing process is highly intricate, it is critical to balance the tradeoff between increasing the number of categories for better quality control and keeping the number of categories low to limit manufacturing complexity. Effectively designing MDPs requires answering complex questions including: How should: a) sort criteria be defined for each component? b) die be combined to achieve desired performance? c) material be routed to minimize cost? 

Intel developed a novel approach – recognized in 2023 with the INFORMS Daniel H. Wagner Prize – to answer these questions that has identified over $500 million in cost savings opportunities over the past two years. The solution utilizes Genetic Algorithms, Monte Carlo Simulations, Machine Learning, and Linear Programming to build a framework that is powerful, flexible, and robust enough to be used for many generations of MDPs to come.